The present invention relates to a data exchange unit for transferring data, commands and so on in packets from a computer to a peripheral device such as optical disk drive, or vice versa, over a transmission line.
In recent years, a telecommunications system complying with the IEEE 1394 standard has attracted much attention as a digital interface for interconnecting together audiovisual (AV) and computer components. The IEEE 1394 system is applicable to communicating not only between computer components, but also between AV components. This is because the IEEE 1394 standard defines both asynchronous and isochronous communications techniques alike. The asynchronous communications technique is applied to transferring computer data, for example, which does not always have to be transmitted in real time but must be highly accurate and reliable. On the other hand, the isochronous communications technique is applied to transferring AV data of a moving picture, for example, from which not so much reliability as real-time transmission is demanded more strongly. Thus, generally speaking, the asynchronous communications technique is preferred in writing computer data on an optical disk drive or reading computer data already recorded from the optical disk drive in accordance with the IEEE 1394 standard, for example. As for communications protocols defined for asynchronous communication between an initiator and a target, Serial Bus Protocol-2 (SBP-2) is under deliberation at the American National Standards Institute (ANSI). The SBP-2 standard defines various task management commands such as Login, QueryLogin and AbortTask and data exchange techniques by indirect addressing using a page table.
A conventional data exchange unit on the target end includes buffers exclusively used for transmission and reception (in this specification, these buffers will be called xe2x80x9ctransmission bufferxe2x80x9d and xe2x80x9creception bufferxe2x80x9d, respectively). The size of each of these buffers is usually equal to the size of a maximum transferable packet. First-in-first-out buffers (FIFOS) implemented as these buffers are called xe2x80x9casynchronous transmission FIFO buffer (ATF)xe2x80x9d and xe2x80x9casynchronous reception FIFO buffer (ARF)xe2x80x9d, respectively. In the prior art, a single central processing unit (CPU) performs various types of processing, including management of the ATF and ARF, in accordance with a program.
In the conventional data exchange unit, however, the CPU often suffers from overload. For example, the CPU has to make request and response packets, write these packets on the ATF, read received packets from the ARF and analyze the header field of a received packet. In addition, the CPU also has to carry out appropriate processing in response to a task management command that has been issued from the initiator. Furthermore, if the initiator has issued a task management command or a request for accessing a configuration read-only memory (config_ROM) or control and status registers (CSR) on the target while data is being transferred, then the CPU must manage suspension or rebooting of the data transfer. Moreover, if the initiator has issued a request for transferring data using a page table, then the CPU has to control the reception of page table data from the initiator and the transmission of the requested data responsive to the page table data on a page-by-page basis. Accordingly, the conventional data exchange unit is disadvantageous in that heavy overheads are necessary for CPU""s firmware processing and that it takes a long time to exchange data.
An object of the present invention is cutting down the heavy overheads involved with CPU""s firmware processing, thereby exchanging data at higher speeds.
To achieve this object, an inventive data exchange unit is adapted to communicate with a counterpart unit through a transmission line using, as a unit, a packet including header and data fields. The exchange unit includes: a transmission buffer; a reception buffer; a transmission-reception buffer; a transmission filter for selectively storing a packet to be transmitted on either the transmission buffer or the transmission-reception buffer depending on the contents of the packet to be transmitted; a reception filter for selectively storing a received packet on either the reception buffer or the transmission-reception buffer depending on the contents of the received packet; a packet processor for making a packet containing information to be transmitted or fetching necessary information from the received packet; a transceiver for converting the packet that has been stored on the transmission buffer or the transmission-reception buffer into an electrical signal to be transmitted through the transmission line or converting another electrical signal received through the transmission line into the packet that will be stored on the reception buffer or the transmission-reception buffer; and a central processing unit (CPU) for activating the packet processor. If a response packet paired with a request packet has been received, then the reception filter stores the response packet received on the transmission-reception buffer and informs the packet processor of response detected. Alternatively, if any other response packet has been received in response to the request packet, then the reception filter stores the received packet on the reception buffer and issues a suspension instruction to the packet processor.
In one embodiment of the present invention, the packet processor preferably includes: a request packet counter for counting the number of request packets provided to the transmission filter; a response packet counter for counting the number of response packets that have been read out from the transmission-reception buffer; and a suspension controller for instructing to stop making new request packets and to inform the CPU of completion of suspension when a count of the response packet counter matches that of the request packet counter in accordance with the suspension instruction. In such an embodiment, if a packet received during a data exchange operation has nothing to do with the operation, then the data exchange will be suspended once a transaction, which is being performed when the packet is received, is completed, and the CPU may use the transmission, reception and transmission-reception buffers freely. More particularly, the packet processor preferably further includes means for accepting a data exchange reboot instruction from the CPU after the CPU has been informed of the completion of suspension.
Another inventive data exchange unit includes: a transmission buffer; a reception buffer; a transmission-reception buffer; a transmission filter for selectively storing a packet to be transmitted on either the transmission buffer or the transmission-reception buffer depending on the contents of the packet to be transmitted; a reception filter for selectively storing a received packet on either the reception buffer or the transmission-reception buffer depending on the contents of the received packet; a packet processor for making a packet containing information to be transmitted or fetching necessary information from the received packet; a transceiver for converting the packet that has been stored on the transmission buffer or the transmission-reception buffer into an electrical signal to be transmitted through the transmission line or converting another electrical signal received through the transmission line into the packet that will be stored on the reception buffer or the transmission-reception buffer; a page table memory for storing page table data, which will be used for indirectly addressing a memory location in the counterpart unit; a packet transmission controller for controlling the packet processor; and a central processing unit (CPU) for activating the packet transmission controller. If the CPU has received a request for transferring data using a page table by way of the reception buffer and has activated the packet transmission controller, then the packet transmission controller instructs the packet processor to make a request packet for acquiring the page table data from the counterpart unit. After the packet processor has acquired the page table data by way of the transmission-reception buffer, the packet transmission controller stores the page table data on the page table memory, and then instructs the packet processor to make another request packet requesting an access to a memory location in the counterpart unit that has been specified by the page table data stored on the page table memory. In the data exchange unit with such a configuration, after the packet transmission controller has been activated, data exchange using the page table is carried out automatically without CPU""s intervention.